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參數(shù)資料
| 型號： | ST90158P9C6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 67/189頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | ST90158P9C6 |
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SERIAL COMMUNICATIONS INTERFACE (SCI)
REGISTER DESCRIPTION (Cont’d)
Bit 6 = SB:
Set Break.
0: Stop the break transmission after minimum
break length.
1: Transmit a break following the transmission of all
data in the Transmitter Shift Register and the
Buffer Register.
Note: The break will be a low level on the transmit-
ter data output for at least one complete word for-
mat. If software does not reset SB before the min-
imum break length has finished, the break condi-
tion will continue until software resets SB. The SCI
terminates the break condition with a high level on
the transmitter data output for one transmission
clock period.
Bit 5 = SA:
Set Address.
If an address/9th data bit mode is selected, SA val-
ue will be loaded for transmission into the Shift
Register. This bit is cleared by hardware after its
load.
0: Indicate it is not an address word.
1: Indicate an address word.
Note: Proper procedure would be, when the
Transmitter Buffer Register is empty, to load the
value of SA and then load the data into the Trans-
mitter Buffer Register.
Bit 4 = RXD:
Receiver DMA Mask.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
receiver End of Block interrupt can occur.
0: Disable Receiver DMA request (the RXDP bit in
the S_ISR register can request an interrupt).
1: Enable Receiver DMA request (the RXDP bit in
the S_ISR register can request a DMA transfer).
Bit 3 = TXD:
Transmitter DMA Mask.
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
transmitter End Of Block interrupt can occur.
0: Disable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request an interrupt).
1: Enable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request a DMA trans-
fer).
Bit 2:0 = PRL[2:0]:
SCI Interrupt/DMA Priority bits.
The
priority
for
the
SCI
is
encoded
with
(PRL2,PRL1,PRL0). Priority level 0 is the highest,
while level 7 represents no priority.
When the user has defined a priority level for the
SCI, priorities within the SCI are hardware defined.
These SCI internal priorities are:
CHARACTER
CONFIGURATION
REGISTER
(CHCR)
R250 - Read/Write
Reset value: undefined
Bit 7 = AM:
Address Mode.
This bit, together with the AMEN bit (in the IDPR
register), decodes the desired addressing/9th data
bit/character match operation. Please refer to the
table in the IDPR register description.
Bit 6 = EP:
Even Parity.
0: Select odd parity (when parity is enabled).
1: Select even parity (when parity is enabled).
Bit 5 = PEN:
Parity Enable.
0: No parity bit.
1: Parity bit generated (transmit data) or checked
(received data).
Note: If the address/9th bit is enabled, the parity
bit will precede the address/9th bit (the 9th bit is
never included in the parity calculation).
Bit 4 = AB:
Address/9th Bit.
0: No Address/9th bit.
1: Address/9th bit included in the character format
between the parity bit and the first stop bit. This
bit can be used to address the SCI or as a ninth
data bit.
Receiver DMA request
highest priority
Transmitter DMA request
Receiver interrupt
Transmitter interrupt
lowest priority
70
AM
EP
PEN
AB
SB1
SB0
WL1
WL0
9
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