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參數(shù)資料
| 型號(hào)： | ST90158P9C6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 59/189頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | ST90158P9C6 |
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SERIAL COMMUNICATIONS INTERFACE (SCI)
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
9.5.7 Input Signals
SIN: Serial Data Input. This pin is the serial data
input to the SCI receiver shift register.
TXCLK: External Transmitter Clock Input. This
pin is the external input clock driving the SCI trans-
mitter. The TXCLK frequency must be greater than
or equal to 16 times the transmitter data rate (de-
pending whether the X16 or the X1 clock have
been selected) and must have a period of at least
twice INTCLK. The use of the TXCLK pin is option-
al.
RXCLK: External Receiver Clock Input. This in-
put is the clock to the SCI receiver when using an
external clock source connected to the baud rate
generator. INTCLK is normally the clock source. A
50% duty cycle is not required for this input, how-
ever, the shortest period must last more than two
INTCLK periods. Use of RXCLK is optional.
DCD: Data Carrier Detect. This input is enabled
only in Synchronous mode; it works as a gate for
the RXCLK clock and informs the MCU that an
emitting device is transmitting a synchronous
frame. The active level can be programmed as 1
or 0 and must be provided at least one INTCLK pe-
riod before the first active edge of the input clock.
9.5.8 Output Signals
SOUT: Serial Data Output. This Alternate Func-
tion output signal is the serial data output for the
SCI transmitter in all operating modes.
CLKOUT: Clock Output. The alternate Function
of this pin outputs either the data clock from the
transmitter in Serial Expansion or Synchronous
modes, or the clock output from the Baud Rate
Generator. In Serial expansion mode it will clock
only the data portion of the frame and its stand-by
state is high: data is valid on the rising edge of the
clock. Even in Synchronous mode CLKOUT will
only clock the data portion of the frame, but the
stand-by level and active edge polarity are pro-
grammable by the user.
When Synchronous mode is disabled (SMEN in
SICR is reset), the state of the XTCLK and OCLK
bits in CCR determine the source of CLKOUT; '11'
enables the Serial Expansion Mode.
When the Synchronous mode is enabled (SMEN
in SICR is set), the state of the XTCLK and OCLK
bits in CCR determine the source of CLKOUT; '00'
disables it for PLM applications.
RTS: Request To Send. This output Alternate
Function is only enabled in Synchronous mode; it
becomes active when the Least Significant Bit of
the data frame is sent to the Serial Output Pin
(SOUT) and indicates to the target device that the
MCU is about to send a synchronous frame; it re-
turns to its stand-by value just after the last active
edge of CLKOUT (MSB transmitted). The active
level can be programmed high or low.
SDS: Synchronous Data Strobe. This output Al-
ternate function is only enabled in Synchronous
mode; it becomes active high when the Least Sig-
nificant Bit is sent to the Serial Output Pins
(SOUT) and indicates to the target device that the
MCU is about to send the first bit for each synchro-
nous frame. It is active high on the first bit and it is
low for all the rest of the frame. The active level
can not be programmed.
9.5.9 Interrupts and DMA
9.5.9.1 Interrupts
The SCI can generate interrupts as a result of sev-
eral conditions. Receiver interrupts include data
pending, receive errors (overrun, framing and par-
ity), as well as address or break pending. Trans-
mitter interrupts are software selectable for either
Transmit Buffer Register Empty (BSN set) or for
Transmit Shift Register Empty (BSN reset) condi-
tions.
Typical usage of the Interrupts generated by the
SCI peripheral are illustrated in Figure 83.
The SCI peripheral is able to generate interrupt re-
quests as a result of a number of events, several
of which share the same interrupt vector. It is
therefore necessary to poll S_ISR, the Interrupt
Status Register, in order to determine the active
trigger. These bits should be reset by the program-
mer during the Interrupt Service routine.
The four major levels of interrupt are encoded in
hardware to provide two bits of the interrupt vector
register, allowing the position of the block of point-
er vectors to be resolved to an 8 byte block size.
The SCI interrupts have an internal priority struc-
ture in order to resolve simultaneous events. Refer
also to Section 9.5.3 SCI Operating Modes for
more details relating to Synchronous mode.
Table 29. SCI Interrupt Internal Priority
Receive DMA Request
Highest Priority
Transmit DMA Request
Receive Interrupt
Transmit Interrupt
Lowest Priority
9
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