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參數(shù)資料
| 型號： | ST7PLU09MAE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 71/124頁 |
| 文件大?。?/td> | 1995K |
| 代理商： | ST7PLU09MAE |
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Power saving modes
ST7LUS5, ST7LU05, ST7LU09
Figure 22.
Halt mode flowchart
1.
WDGHALT is an option bit. See option bytes in Section 14.1.1: Flash configuration for more details.
2.
Peripheral clocked with an external clock source can still be active.
3.
Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 15: Interrupt mapping on page 39 for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5.
The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering Halt mode.
Halt mode recommendations
●
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●
When using an external interrupt to wake up the microcontroller, re-initialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
HALT INSTRUCTION
RESET
INTERRUPT(3)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS(2)
IBIT
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
X(4)
ON
CPU
OSCILLATOR
PERIPHERALS
IBITS
ON
X(4)
ON
64 CPU CLOCK CYCLE
DELAY(5)
WATCHDOG
ENABLE
DISABLE
WDGHALT(1)
0
WATCHDOG
RESET
1
(Active Halt disabled)
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