參數(shù)資料
型號: ST7PLITE05Y0B3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP16
封裝: 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù): 71/115頁
文件大?。?/td> 781K
代理商: ST7PLITE05Y0B3
ST7FLITE0
59/115
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure 39).
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 39, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Figure 39. Data Clock Timing Diagram
SCK
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MISO
(frommaster)
MOSI
(fromslave)
SS
(to slave)
CAPTURESTROBE
CPHA =1
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit4
Bit3
Bit2
Bit1
LSBit
MISO
(frommaster)
MOSI
SS
(toslave)
CAPTURESTROBE
CPHA =0
Note:
Thisfigure should not beused asa replacement for parametricinformation.
Refer to the Electrical Characteristics chapter.
(fromslave)
(CPOL=1)
SCK
(CPOL =0)
SCK
(CPOL =1)
SCK
(CPOL =0)
1
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