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| 型號(hào)： | ST7PLITE05Y0B3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 46/115頁(yè) |
| 文件大?。?/td> | 781K |
| 代理商： | ST7PLITE05Y0B3 |
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ST7FLITE0
36/115
POWER SAVING MODES (Cont’d)
9.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the LTCSR/ATCSR reg-
ister status as shown in the following table:.
9.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when active halt mode is enabled.
The MCU can exit ACTIVE-HALT mode on recep-
tion of a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 32) or a RESET.
– When exiting ACTIVE-HALT mode by means of
a RESET, a 256 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation
by fetching the reset vector which woke it up (see
Figure 24).
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 24).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Caution: As soon as ACTIVE-HALT is enabled,
executing a HALT instruction while the Watchdog
is active does not generate a RESET if the
WDGHALT bit is reset.
This means that the device cannot spend more
than a defined delay in this power saving mode.
Figure 23. ACTIVE-HALT Timing Overview
Figure 24. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the Lite Timer RTC interrupt and some
specific interrupts can exit the MCU from ACTIVE-
HALT mode (such as external interrupt). Refer to
Table 7, “Interrupt Mapping,” on page 32 for more
details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
LTCSR
TBIE bit
ATCSR
OVFI E
bit
ATCSR
CK1 bit
ATCSR
CK0 bit
Meaning
0
xx0
ACTIVE-HALT
mode disabled
00
x
011
1
xxx
ACTIVE-HALT
mode enabled
x1
0
1
HALT
RUN
256 CPU
CYCLE DELAY 1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
FETCH
VECTOR
ACTIVE
[Active Halt Enabled]
HALT INSTRUCTION
RESET
INTERRUPT 3)
Y
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
I BIT
ON
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS 2)
I BIT
ON
OFF
X 4)
ON
CPU
OSCILLATOR
PERIPHERALS
I BITS
ON
X 4)
ON
256 CPU CLOCK CYCLE
DELAY
(Active Halt enabled)
1
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| ST7PLITE05Y0B6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI |
| ST7PLITE05Y0B6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE05Y0M6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI |
| ST7PLITE05Y0M6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7PLITE05Y0U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
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