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參數(shù)資料
| 型號： | ST7PLITE05Y0B3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 63/115頁 |
| 文件大?。?/td> | 781K |
| 代理商： | ST7PLITE05Y0B3 |
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ST7FLITE0
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12-BIT AUTORELOAD TIMER (Cont’d)
Figure 34. PWM Signal Example
Output Compare Mode
To use this function, the OE bit must be 0. Soft-
ware must then write a 12-bit value in the DCR0H
and DCR0L registers. This value will be loaded im-
mediately (without waiting for an OVF event).
The DCR0H must be written first, the output com-
pare function starts only when the DCR0L value is
written.
When the 12-bit upcounter (CNTR) reaches the
value stored in the DCR0H and DCR0L registers,
the CMPR0 bit in the PWM0CSR register is set
and an interrupt request is generated if the CMPIE
bit is set.
Note: The output compare function is only availa-
ble for DCRx values other than 0 (reset value).
11.2.4 Low Power Modes
11.2.5 Interrupts
Note: The interrupt events are connected to sepa-
rate interrupt vectors (see Interrupts chapter).
They generates an interrupt if the enable bit is set
in the ATCSR register and the interrupt mask in
the CC register is reset (RIM instruction).
COUNTER
PWM0
OUTPUT
t
WITH
OE0=1
AND
OP0=0
FFDh
FFEh
FFFh
FFDh
FFEh
FFFh
FFDh
FFEh
DCR0=FFEh
ATR= FFDh
fCOUNTER
Mode
Description
WAIT
No effect on AT timer
HALT
AT timer halted.
Interrupt
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Overflow
Event
OVFF
TBIE
Yes
CMP Event
CMPFx
CMPIE
Yes
No
1
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