參數(shù)資料
型號(hào)： ST7PL05Y0MB/XXXTRE
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.150 INCH WIDTH, PLASTIC, LEAD FREE, SOP-16
文件頁(yè)數(shù)： 26/106頁(yè)
文件大?。?/td> 1990K
代理商： ST7PL05Y0MB/XXXTRE
ST7L05, ST7L09
26/104
SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The reset sequence manager includes two RE-
SET sources as shown in Figure 14:
■ External RESET source pulse
■ Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to Section 12.2.1 on page 70 for further details.
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of three
phases as shown in Figure 13:
■ Active Phase depending on the RESET source
■ 256 CPU clock cycle delay
■ RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid-
unwanted behavior.
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilize and ensures that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is two
clock cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of tSTARTUP (see
Figure 13. RESET Sequence Phases
Figure 14. ST7L0x Reset Block Diagram
RESET
Active Phase
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
RESET
RON
VDD
INTERNAL
RESET
PULSE
GENERATOR
FILTER
Note 1: See “Illegal Opcode Reset” on page 70. for more details on illegal opcode reset conditions.
WATCHDOG RESET
ILLEGAL OPCODE RESET1)
1
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