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| 型號： | ST7LITE10F1M6 |
| 英文描述： | FUSE PULLER/TESTERFUSE PULLER/TESTER; Depth, external:15mm; Length:60mm; Voltage rating, AC:24V; Voltage rating, DC:24V; Width, external:20mm |
| 中文描述： | ST7LITE1 - 8單電壓閃存EEPROM的MEMORY.DATA位MCU。 ADC的。 4定時器。的SPI |
| 文件頁數(shù)： | 44/122頁 |
| 文件大?。?/td> | 1716K |
| 代理商： | ST7LITE10F1M6 |
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ST7LITE0, ST7SUPERLITE
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1
I/O PORTS
(Cont’d)
CAUTION
: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
WARNING:
The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
10.3 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to
Section 13.8
.
10.4 LOW POWER MODES
10.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
10.6 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in
Figure 29
Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 29. Interrupt I/O Port State Transitions
The I/O port register configurations are summa-
rised as follows.
Table 11. Port Configuration
Mode
Description
WAIT
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
HALT
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
External interrupt on
selected external
event
-
DDRx
ORx
Yes
Yes
01
floating/pull-up
interrupt
INPUT
00
floating
(reset state)
INPUT
10
open-drain
OUTPUT
11
push-pull
OUTPUT
XX
= DDR, OR
Port
Pin name
Input (DDR=0)
OR = 0
floating
floating
floating
floating
floating
floating
floating
Output (DDR=1)
OR = 0
open drain
open drain
open drain
open drain
open drain
open drain
open drain
OR = 1
OR = 1
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
Port A
PA7
PA6:1
PA0
PB4
PB3
PB2:1
PB0
pull-up interrupt
pull-up
pull-up interrupt
pull-up
pull-up interrupt
pull-up
pull-up interrupt
Port B
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