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參數(shù)資料
| 型號： | ST7FL09Y0MBE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 56/104頁 |
| 文件大?。?/td> | 2151K |
| 代理商： | ST7FL09Y0MBE |
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7L05, ST7L09
55/104
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see Figure 34)
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
–SS internal must be held high continuously
In Slave mode:
Two cases depend on the data/clock timing rela-
tionship (see Figure 33):
If CPHA = 1 (data latched on 2nd clock edge):
–SS internal must be held low during the entire
transmission. This implies that in single slave
applications the SS pin either can be tied to
VSS, or made free for standard I/O by manag-
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
If CPHA = 0 (data latched on 1st clock edge):
–SS internal must be held low during byte
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see Section 11.3.5.3).
Figure 33. Generic SS Timing Diagram
Figure 34. Hardware/Software Slave Select Management
MOSI/MISO
Master SS
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Byte 1
Byte 2
Byte 3
1
0
SS internal
SSM bit
SSI bit
SS external pin
1
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