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參數(shù)資料
| 型號： | ST7FL09Y0MBE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 15/104頁 |
| 文件大?。?/td> | 2151K |
| 代理商： | ST7FL09Y0MBE |
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Obsolete
Product(s)
- Obsolete
Product(s)
ST7L05, ST7L09
18/104
DATA EEPROM (Cont’d)
5.4 POWER SAVING MODES
Wait mode
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler or when the microcontroller enters Active Halt
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
Active Halt mode
Refer to Wait mode.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT = 1, then the
data bus will not be driven.
If a write access occurs while E2LAT = 0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by RESET
action), the integrity of the data in memory will not
be guaranteed.
5.6 DATA EEPROM READ-OUT PROTECTION
The read-out protection is enabled through an op-
tion bit (see option byte section).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out (including a re-write protection).
In Flash devices, when this protection is removed
by reprogramming the Option Byte, the entire Pro-
gram memory and EEPROM is first automatically
erased.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 8. Data EEPROM Programming Cycle
LAT
ERASE CYCLE
WRITE CYCLE
PGM
tPROG
READ OPERATION NOT POSSIBLE
WRITE OF
DATA
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
LATCHES
1
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| ST7FL15F1MATRE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI |
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