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參數(shù)資料
| 型號(hào)： | ST72T734J6B1 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C |
| 中文描述： | 8位USB單片機(jī)的顯示器，高達(dá)60K章檢察官辦公室，每1000內(nèi)存，模數(shù)轉(zhuǎn)換器，定時(shí)器，同步，材質(zhì)單元，脈寬調(diào)制/的BRM，的H / W DDC的 |
| 文件頁(yè)數(shù)： | 18/144頁(yè) |
| 文件大?。?/td> | 1280K |
| 代理商： | ST72T734J6B1 |
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DDC INTERFACE (Cont’d)
DDC1/2B CONTROL REGISTER (DCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = Reserved.
Forced by hardware to 0.
Bit 5 = EDF
End of Download interrupt Flag.
This bit is set by hardware and cleared by
software.
0: Download not started or not completed yet.
1: Download completed. Last byte of data struc-
ture (relative address 7Fh or FFh) has been
stored in RAM.
Bit 4 = EDE
End of Download interrupt Enable.
This bit is set and cleared by software.
0: Interrupt disabled.
1: A DDC1/2B interrupt is generated if EDF bit is
set.
Bits 6, 3:2 = CF[2:0]
Configuration bits.
These bits are set and cleared by software only
when the peripheral is disabled (HWPE = 0). They
define which EDID structure version is used and
which Device Addresses are recognized as shown
in the following table:
Bit 1 = WP
Write Protect.
This bit is set and cleared by software.
0: Enable writes to the RAM.
1: Disable DMA write transfers and protect the
RAM content. CPU writes to the RAM are not
affected.
Bit 0= HWPE
Peripheral Enable.
This bit is set and cleared by software.
0: Release the SDA port pin and ignore Vsync
and SCL port pins. The other bits of the DCR
and the content of the AHR are left un-
changed.
1: Enable the DDC Interface and respond to the
DDC1/DDC2B protocol.
ADDRESS POINTER HIGH REGISTER (AHR)
Read / Write
Reset Value: see Register Map
AHR contains the 8 MSB’s of the 16-bit address
pointer. It therefore defines the location of the 256-
byte block containing the data structure within the
CPU address space.
Note: AHR0 is ignored when CF[1:0] = 10 (P&D+ v2
mode) to allow non-overlapping 128-byte and 256-
byte data structures.
70
0
CF2
EDF
EDE
CF1
CF0
WP
HWPE
70
MSB
LSB
CF[2:0] Bit
Values
EDID version used
DDC1 Mode support / Transition Mode support
DDC2B Addresses Recognized
000
DDC v2
Yes (128b EDID) / Yes
128b-EDID
@A0h/A1h
001
P&D
No
256b-EDID
@ A2h/A3h
010
v2 + P&D
Yes (128b EDID) / Yes
128b-EDID
@A0h/A1h
256b-EDID
@ A2h/A3h
011
FPDI-2
No
256b-EDID
@ A6h/A7h
100
DDC v2
No
128b-EDID
@A0h/A1h
101
Reserved
d sd
110
v2 + P&D
No
128b-EDID
@A0h/A1h
256b-EDID
@ A2h/A3h
111
Reserved
d sd
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