參數(shù)資料
型號： ST72T734J6B1
廠商： 意法半導體
元件分類： ADC
英文描述： 8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
中文描述： 8位USB單片機的顯示器，高達60K章檢察官辦公室，每1000內存，模數(shù)轉換器，定時器，同步，材質單元，脈寬調制/的BRM，的H / W DDC的
文件頁數(shù)： 109/144頁
文件大?。?/td> 1280K
代理商： ST72T734J6B1
ST72774/ST727754/ST72734
67/144
SYNC PROCESSOR (SYNC) (Cont’d)
4.4.9 Corrector Mode
In this mode, you can perform the following
functions:
– Inhibit pre/post equalization pulses
This removes all pre/post equalization pulses
on the HSYNCO signal.
The inhibition starts on the falling edge of
HSYNCO and lasts for (((HGENR+1)/4)-2)
s. The decrease of 2s (one minimum pulse
width) avoids the removal of the next pulse of
HSYNCO.
Procedure:
1. HSYNCO and VSYNCO polarities must be
positive.
2. Measure the low level of HSYNCO.
3. Set the 2FHINH bit in the CFGR register.
– Extend VSYNCO pulse width by several scan
lines
This function can be also used to extend the
video blanking signal.
Procedure:
1. HSYNCO and VSYNCO polarities must be
positive.
2. Set the 2FHINH bit in the CFGR register
only if some pre/post equalizations pulses
are detected. (2FHLAT, 2FHDET flags).
3. The extension will be the number of
HSYNCO periods set in the VGENR
register.
4. Reset the VCORDIS bit in the POLR
register.
– Extend VSYNCO width during all post equaliza-
tion pulses.
This function extends the VSYNCO pulse
width when post equalization pulses are
detected (2FHDET bit in the POLR register
and 2FHLAT bit in the LATR register).
Procedure:
1. HSYNCO and VSYNCO polarities must be
positive.
2. Set the 2FHINH bit in the CFGR register to
remove pre/post equalization pulses.
3. Measure the low level of HSYNCO.
4. Update HGENR =(FFh - (HGENR + 1)) + 4
to add tolerance
5. Write VGENR > 0.
6. Reset the VCORDIS bit in the POLR
register
7. Set the VEXT bit in the CFGR register.
– Extend VSYNCO pulse width during pre and
post equalization pulses (for test only).
This function allows extending the VSYNCO
pulse width as long as equalization pulses are
detected. (VSYNCO = VSYNCO + 2FHDET).
Procedure:
1. HSYNCO and VSYNCO polarities must be
positive.
2. Set the 2FHINH bit in the CFGR register to
remove pre/post equalization pulses.
3. Measure the low level of HSYNCO.
4. Update HGENR =(FFh - (HGENR + 1)) + 4.
5. Write VGENR > 0.
6. Reset the VCORDIS bit in the POLR register.
7. Set the VEXT bit in the CFGR register.
8. Set the 2FHEN bit in the ENR register.
Notes:
1. When corrector mode is active, the free-running
frequencies generator and analyzer mode must
be disabled.
(HVGEN=0 in ENR register, HACQ=0, VACQ=0
in the CFGR register).
2. If VGENR=0, all VSYNCO correction functions
are disabled except the 2FHEN bit which must
be cleared if VGENR = 0 or VCORDIS = 1.
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