參數(shù)資料
型號: ST72T2311R9T6
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述: 8位嵌套中斷,EEPROM存儲器,模數(shù)轉(zhuǎn)換器,16位定時器,8位PWM藝術(shù),SPI和脊髓損傷,微控制器的CAN接口
文件頁數(shù): 5/164頁
文件大小: 1043K
代理商: ST72T2311R9T6
ST72311R, ST72511R, ST72512R, ST72532R
102/164
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 52).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 52).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
Bit 7:6= SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bit 5:3 = SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0]
SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
70
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
70
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
PR Prescaling factor
SCP1
SCP0
10
0
30
1
41
0
13
1
TR dividi ng factor
SCT2
SCT1
SCT0
1
000
2
001
4
010
8
011
16
100
32
101
64
110
128
1
RR dividi ng factor
SCR2
SCR1
SCR0
1
000
2
001
4
010
8
011
16
100
32
101
64
110
128
1
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