參數(shù)資料
型號(hào)： ST72T2311R9T6
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述： 8位嵌套中斷，EEPROM存儲(chǔ)器，模數(shù)轉(zhuǎn)換器，16位定時(shí)器，8位PWM藝術(shù)，SPI和脊髓損傷，微控制器的CAN接口
文件頁數(shù)： 107/164頁
文件大小： 1043K
代理商： ST72T2311R9T6
ST72311R, ST72511R, ST72512R, ST72532R
47/164
MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = IPA
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSI-
TIVITY” on page 45 and the description of the IS2x
bits of the MISCR1 register for more details.
Bit 6 = IPB
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSI-
TIVITY” on page 45 and the description of the IS1x
bits of the MISCR1 register for more details.
Bit 5:4 = BC[1:0]
Beep control
These 2 bits select the PF1 pin beep capability.
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
Bit 3 = TLIS
TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
Bit 2 = TLIE
TLI enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
Bit 1 = SSM
SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode (PC7), the level of the SPI SS signal is
read from the SSI bit.
Bit 0 = SSI
SS internal mode
This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.
70
IPA
IPB
BC1
BC0
TLIS
TLIE
SSM
SSI
BC1
BC0
Beep mode with fOSC=16MHz
0
Off
0
1
~2-KHz
Output
Beep signal
~50% duty cycle
1
0
~1-KHz
1
~500-Hz
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