參數(shù)資料
型號: ST72T2311R6T6S
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES
中文描述: 8位嵌套中斷,EEPROM存儲(chǔ)器,模數(shù)轉(zhuǎn)換器,16位定時(shí)器,8位PWM藝術(shù),SPI和脊髓損傷,微控制器的CAN接口
文件頁數(shù): 103/164頁
文件大?。?/td> 1043K
代理商: ST72T2311R6T6S
ST72311R, ST72511R, ST72512R, ST72532R
43/164
I/O PORTS (Cont’d)
8.5.1 Register Description
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0]
Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DD[7:0]
Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B, C, D, E or F.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = O[7:0]
Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: pull-up input with or without interrupt
Output mode:
0: output open drain (with P-Buffer unactivated)
1: output push-pull
70
D7
D6
D5
D4
D3
D2
D1
D0
70
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
70
O7
O6
O5
O4
O3
O2
O1
O0
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