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參數資料
| 型號： | ST72T213G1B6 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS |
| 中文描述： | 8位微控制器有4到8K的光碟/雙層/存儲器，256字節(jié)RAM，ADC的，水分散粒劑，SPI和1或2定時器 |
| 文件頁數： | 55/84頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ST72T213G1B6 |
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ST72101/ST72212/ST72213
SERIAL PERIPHERAL INTERFACE (Cont’d)
4.4.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000xxxx (0xh)
Bit 7 = SPIE
Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1
or MODF=1 in the SR register
Bit 6 = SPE
Serial peripheral output enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 4.4.4.5 Master Mode Fault).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.
Bit 5 = SPR2
Divider Enable.
this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 17.
0: Divider by 2 enabled
1: Divider by 2 disabled
Bit 4 = MSTR
Master.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 4.4.4.5 Master Mode Fault).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.
Bit 3 = CPOL
Clock polarity.
This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 2 = CPHA
Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Bit 1:0 = SPR[1:0]
Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.
These 2 bits have no effect in slave mode.
Table 17. Serial Peripheral Baud Rate
70
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Serial Clock
SPR2
SPR1
SPR0
fCPU/2
1
0
fCPU/8
0
fCPU/16
0
1
fCPU/32
1
0
fCPU/64
0
1
0
fCPU/128
0
1
59
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ST72T213G1M6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72T251G1B6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI/I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72T251G1M6 | 功能描述:8位微控制器 -MCU RO 511-ST72C254G1M6 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72T251G2B6 | 功能描述:8位微控制器 -MCU OTP EPROM 8K SPI/I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72T251G2M6 | 功能描述:8位微控制器 -MCU OTP EPROM 8K SPI/I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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