參數(shù)資料
型號(hào): ST72T213G1B6
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
中文描述: 8位微控制器有4到8K的光碟/雙層/存儲(chǔ)器,256字節(jié)RAM,ADC的,水分散粒劑,SPI和1或2定時(shí)器
文件頁數(shù): 32/84頁
文件大?。?/td> 531K
代理商: ST72T213G1B6
38/84
ST72101/ST72212/ST72213
16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare
In this section, the index,
i, may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (
fCPU/(CC1.CC0)).
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OC
iE bit if an output is needed then the
OCMP
i pin is dedicated to the output compare i
function.
– Select the timer clock (CC1-CC0) (see Table
15).
And select the following in the CR1 register:
– Select the OLVL
i bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found:
– OCF
i bit is set.
– The OCMP
i pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
The OCiR register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
t
= Desired output compare period (in sec-
onds)
fCPU
= Internal clock frequency
PRESC = Timer prescaler factor (2, 4 or 8 de-
pending on CC1-CC0 bits, see Table
15)
Clearing the output compare interrupt request is
done by:
1. Reading the SR register while the OCF
i bit is
set.
2. An access (read or write) to the OC
iLR register.
The following procedure is recommended to pre-
vent the OCF
i bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OC
iHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCF
i bit, which may be already set).
– Write to the OC
iLR register (enables the output
compare function and clears the OCF
i bit).
Notes:
1. After a processor write cycle to the OC
iHR reg-
ister, the output compare function is inhibited
until the OC
iLR register is also written.
2. If the OC
iE bit is not set, the OCMPi pin is a
general I/O port and the OLVL
i bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the clock is divided by 2, OCF
i and
OCMP
i are set while the counter value equals
the OC
iR register value (see Figure 29, on
page 39). This behaviour is the same in OPM
or PWM mode.
When the clock is divided by 4, 8 or in external
clock mode, OCF
i and OCMPi are set while the
counter value equals the OC
iR register value
plus 1 (see Figure 30, on page 39).
4. The output compare functions can be used both
for generating external events on the OCMP
i
pins even if the input capture mode is also
used.
5. The value in the 16-bit OCiR register and the
OLV
i bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
MS Byte
LS Byte
OC
iROCiHR
OC
iLR
OCiR=
t * fCPU
PRESC
38
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