參數(shù)資料
型號: ST72T213G1B6
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
中文描述: 8位微控制器有4到8K的光碟/雙層/存儲器,256字節(jié)RAM,ADC的,水分散粒劑,SPI和1或2定時(shí)器
文件頁數(shù): 30/84頁
文件大?。?/td> 531K
代理商: ST72T213G1B6
36/84
ST72101/ST72212/ST72213
16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
In this section, the index,
i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAP
i pin (see figure 5).
IC
i register is a read-only register.
The active transition is software programmable
through the IEDG
i bit of the Control Register (CRi).
Timing resolution is one count of the free running
counter: (
fCPU/(CC1.CC0)).
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC1-CC0) (see Table
15).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from both the ICAP1 pin or
the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
When an input capture occurs:
– ICF
i bit is set.
– The IC
iR register contains the value of the free
running counter on the active transition on the
ICAP
i pin (see Figure 27).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request is
done in two steps:
1. Reading the SR register while the ICF
i bit is set.
2. An access (read or write) to the IC
iLR register.
Notes:
1. After reading the IC
iHR register, transfer of
input capture data is inhibited until the IC
iLR
register is also read.
2. The IC
iR register always contains the free run-
ning counter value which corresponds to the
most recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the output
compare mode.
4. In One pulse Mode and PWM mode only the
input capture 2 can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture process.
6. Moreover if one of the ICAP
i pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
7. The TOF bit can be used with interrupt in order
to measure event that go beyond the timer
range (FFFFh).
MS Byte
LS Byte
ICiR
IC
iHR
IC
iLR
36
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