參數(shù)資料
型號: ST72F324J4
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
中文描述: 8位微控制器嵌套中斷。閃光。 10位ADC。 4定時器。的SPI。 SCI接口
文件頁數(shù): 81/161頁
文件大?。?/td> 2070K
代理商: ST72F324J4
ST72324
26/161
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET pulse is shorter than
tw(RSTL)out (see short ext. Reset in Figure 14), the
signal on the RESET pin may be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in Figure 14). Starting from the external RE-
SET pulse recognition, the device RESET pin acts
as an output that is pulled low during at least
tw(RSTL)out.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until VDD is over the minimum
level specified for the selected fOSC frequency.
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
s
Power-On RESET
s
Voltage Drop RESET
The device RESET pin acts as an output that is
pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 14.
The LVD filters spikes on VDD larger than tg(VDD) to
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 14.
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tw(RSTL)out.
Figure 14. RESET Sequences
VDD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
VIT+(LVD)
VIT-(LVD)
th(RSTL)in
tw(RSTL)out
RUN
th(RSTL)in
ACTIVE
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
tw(RSTL)out
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
DELAY
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ST72F324J6 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
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