參數(shù)資料
型號： ST72E734J6D0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42
封裝： CERAMIC, SDIP-42
文件頁數(shù)： 63/144頁
文件大?。?/td> 1280K
代理商： ST72E734J6D0
ST72774/ST727754/ST72734
25/144
3.4 POWER SAVING MODES
3.4.1 WAIT Mode
This mode is a low power consumption mode. The
WFI instruction places the MCU in WAIT mode:
The internal clock remains active but all CPU
processing
is
stopped;
however,
all
other
peripherals are still running.
Note: In WAIT mode, DMA accesses (DDC, USB)
are possible.
During WAIT mode, the I bit in the condition code
register is cleared to enable all interrupts, which
causes the MCU to exit WAIT mode, causes the
corresponding interrupt vector to be fetched, the
interrupt routine to be executed and normal
processing to resume. A reset causes the program
counter to fetch the reset vector and processing
starts as for a normal reset.
Table 5 gives a list of the different sections
affected by the low power modes. For detailed
information on a particular device, please refer to
the corresponding part.
3.4.2 HALT Mode
The HALT mode is the MCU lowest power
consumption mode. Meanwhile, the HALT mode
also stops the oscillator stage completely which is
the most critical condition in CRT monitors.
For this reason, the HALT mode has been disabled
and its associated HALT instruction is now
considered as illegal and will generate a reset.
Figure 14. WAIT Flow Chart
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
Y
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
CLEARED
OFF
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
SET
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT
4096 CPU CLOCK
CYCLES DELAY
IF RESET
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
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