參數(shù)資料
型號： ST72E734J6D0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42
封裝： CERAMIC, SDIP-42
文件頁數(shù)： 122/144頁
文件大?。?/td> 1280K
代理商： ST72E734J6D0
ST72774/ST727754/ST72734
79/144
4.6 USB INTERFACE (USB)
4.6.1 Introduction
The USB Interface implements a low-speed
function interface between the USB and the ST7
microcontroller. It is a highly integrated circuit
which
includes
the
transceiver,
3.3
voltage
regulator, SIE and DMA. No external components
are needed apart from the external pull-up on
USBDM for low speed recognition by the USB
host.
4.6.2 Main Features
s
USB Specification Version 1.0 Compliant
s
Supports Low-Speed USB Protocol
s
Two or Three Endpoints (including default one)
depending on the device (see device feature list
and register map)
s
CRC
generation/checking,
NRZI
encoding/
decoding and bit-stuffing
s
USB Suspend/Resume operations
s
DMA Data transfers
s
On-Chip 3.3V Regulator
s
On-Chip USB Transceiver
4.6.3 Functional Description
The block diagram in Figure 50, gives an overview
of the USB interface hardware.
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www.usb.org.
Serial Interface Engine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The
SIE
processes
tokens,
handles
data
transmission/reception,
and
handshaking
as
required by the USB standard. It also performs
frame formatting, including CRC generation and
checking.
Endpoints
The
Endpoint
registers
indicate
if
the
microcontroller is ready to transmit/receive, and
how many bytes need to be transmitted.
DMA
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place, using DMA. At the end of the transaction, an
interrupt is generated.
Interrupts
By
reading
the
Interrupt
Status
register,
application software can know which USB event
has occurred.
Figure 50. USB block diagram
CPU
MEMORY
Transceiver
3.3V
Voltage
Regulator
SIE
ENDPOINT
DMA
INTERRUPT
Address,
and interrupts
USBDM
USBDP
USBVCC
6 MHz
REGISTERS
data busses
USBGND
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