參數(shù)資料
型號(hào)： ST72E734J6D0
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42
封裝： CERAMIC, SDIP-42
文件頁數(shù)： 119/144頁
文件大?。?/td> 1280K
代理商： ST72E734J6D0
ST72774/ST727754/ST72734
76/144
TIMING MEASUREMENT UNIT (Cont’d)
– Obtain the minimum number of horizontal
sync output pulses (V2) between the last fall-
ing edge of the active video input (AV) and the
rising edge of the vertical sync signal (VSYN-
CO or VFBACK) during two 2 consecutive
frames.
The
H_V
bit
selects
horizontal
or
vertical
measurement. This selection should be made prior
to starting the measurement by setting the START
bit. This bit is set by software but only cleared by
hardware at the end of the measurement.
When the measurement is finished (rising edge of
AV, horizontal or vertical sync signals), the results
(T1,T2) are transferred into the corresponding
registers (H1,H2) or (V1,V2).
Note: The values of the H1/H2 or V1/V2 registers are
available only at the end of a measurement (after
the START bit has been cleared).
4.5.3.1 Horizontal Measurement
When the H_V bit = 1, and when the START bit is
set by software, the measurement starts after the
next vertical sync pulse. The TMU searches the
minimum values of H1 and H2 until the rising edge
of the next following vertical sync pulse. The
START bit is then cleared by hardware.
The values of the H1 and H2 registers are
available only at the end of a measurement, in
other words when the START bit is at 0.
4.5.3.2 Vertical Measurement
When the H_V bit = 0 and, when the START bit is
set by software, the TMU measures the minimum
V1 and V2 values during 2 consecutive vertical
frames. The START bit is then cleared by
hardware.
4.5.3.3 Special cases
– If an overflow of the counter occurs during any of
the measurements, the measured T1 or T2 val-
ues will be 7FFh.
– If the AV signal is always low (no active video),
the measured T1 or T2 values will also be 7FFh.
– If T1
≤ 0 (AV already high when the falling edge
of the sync signal occurs), the measured T1 val-
ue will be fixed to 1.
– If T2
≤ 0 (AV still high when the rising edge of the
sync signal occurs), a specific T2 value will be re-
turned.
Note: Refer to Application Note AN1183 for further de-
tails.
Figure 48. Horizontal Measurement
Figure 49. Vertical Measurement
HSYNCO or
AV
H1
H2
H1 and H2 measured in oscillator clock periods
Note: HSYNCO or HFBACK must be positive.
HFBACK
VSYNCO or
AV
V1
V2
V1 and V2 measured in horizontal pulses
Note: VSYNCO or VFBACK must be positive.
VFBACK
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