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參數(shù)資料
| 型號(hào)： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁(yè)數(shù)： | 67/189頁(yè) |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
159/189
MSCI PARALLEL INTERFACE (Cont’d)
REED SOLOMON CONTROL STATUS REGISTER (RCSR)
Read / Write
Reset Value: 0100 0000 0000 0000 (4000h).
Bit 15 = DOFF Decoder Output FIFO Full.
This bit is set by hardware when the decoder out-
put FIFO is full and reset by hardware when MSCI
software reads data from this FIFO through the
RDFDR register.
0: RS Decoder output FIFO not full.
1: RS Decoder output FIFO full.
Bit 14 = DOFE Decoder Output FIFO Empty.
This bit is set by hardware when the 8th word is
read by MSCI software from the decoder output
FIFO through the RDFDR register. It is reset by
hardware when FIFO is full again.
0: RS Decoder output FIFO not empty.
1: RS Decoder output FIFO empty.
Bit 13 = DLWR Decoder Last Word Read.
This bit is set by hardware when the last word is
read from the decoder output FIFO. It is reset by
hardware when a word that is not the last of a 512-
byte packet is read from the decoder output FIFO.
0: RS Decoder last word not read.
1: RS Decoder last word read.
Bit 12 = DRR Decoder Ready to Receive.
This bit is set and reset by hardware. It indicates
whether the decoder is ready to be used or not.
Data must not be sent to the decoder if DRR=0.
refer to Section 17.8 for more information.
0: RS Decoder not ready to receive.
1: RS Decoder ready to receive.
Bit 11 = DEFV Decoder Error Flag Valid.
This bit is set by hardware when the error flag is
valid. This happens a few MSCI cycles after the
decoder received a complete packet. It is reset by
hardware when the first symbol of the next data
packet is received by the decoder.
0: RS Decoder error flag is valid.
1: RS Decoder error flag is not valid.
Bit 10 = DEF Decoder Error Flag.
This bit is set by hardware when an error is detect-
ed in the current data packet. This flag is signifi-
cant only when DEFV bit is set. It is reset by hard-
ware when the first symbol of the next data packet
is received by the decoder.
0: No error detected by RS decoder.
1: Error(s) detected by RS decoder.
Bit 9 = DEOC Decoder End Of Correction.
This bit is set by hardware when the correction al-
gorithm is finished and when all words of the
512byte data packet are read from the decoder
output. It is reset by hardware when the first sym-
bol of the next data packet is received by the de-
coder.
0: RS Decoder correction not finished.
1: RS Decoder correction finished.
Bit 8 = DUE Decoder Uncorrectable Error.
This bit is set by hardware when the decoder de-
tects an error that can not be recovered. This flag
is significant only when DEOC=1 (after full decod-
ing process including the reading of the complete
decoded data packet from the decoder output
FIFO. It is reset by hardware when the first symbol
of the next data packet is received by the decoder.
0: No uncorrectable error detected by RS decoder.
1: Uncorrectable error(s) detected by RS decoder.
Bit [7:5] = DNE[2:0] Decoder Number of Errors.
These bits are set by hardware by the decoder to
give the number of errors detected. This flag is sig-
nificant only when DEOC=1 and if the DUE flag is
not set. It is reset by hardware when the first sym-
bol of the next data packet is received by the de-
coder.
15
8
7
0
DOFF
DOFE DLWR
DRR
DEFV
DEF
DEOC
DUE
DNE[2] DNE[1] DNE[0]
DE
EPR
FD
EE
DIFF
DNE[2]
DNE[1]
DNE[0]
Number of errors
0
00
1
01
0
2
01
1
3
10
0
4
1
0
1
N/A
1
0
N/A
1
N/A
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