參數(shù)資料
型號： ST7263BK1B/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, LEAD FREE, SHRINK, PLASTIC, DIP-32
文件頁數(shù)： 43/140頁
文件大?。?/td> 1423K
代理商： ST7263BK1B/XXX
ST7263B
137/140
16 IMPORTANT NOTES
16.1 UNEXPECTED RESET FETCH
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
16.2 HALT MODE POWER CONSUMPTION
WITH ADC ON
If the A/D converter is being used when Halt mode
is entered, the power consumption in Halt Mode
may exceed the maximum specified in the datash-
eet.
Workaround
Switch off the ADC by software (ADON=0) before
executing a HALT instruction.
16.3 SCI WRONG BREAK DURATION
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy
of
19200
baud
(fCPU=8MHz
and
SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
16.4 I2C MULTIMASTER
In multimaster configurations, if the ST7 I2C re-
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication
16.5 USB Behavior with LVD Disabled
On 4K and 8K ROM devices (ST7263BK1M1,
ST72BK2M1, ST7263BKB1, ST7263BK2B1 only)
if the LVD is disabled, the USB is disabled by hard-
ware. So, the LVD is forced by ST to 0 (LVD ena-
bled). Refer to the ST7263B option list for details.
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