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參數(shù)資料
| 型號(hào)： | ST7260E2M1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 76/118頁 |
| 文件大?。?/td> | 2304K |
| 代理商： | ST7260E2M1/XXX |
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ST7260
60/117
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.3.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in Figure 35 It contains 6 dedicated reg-
isters:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
Refer to the register descriptions in Section 11.3.7
for the definitions of each bit.
11.3.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see Figure 35).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 36. Word Length Programming
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
Start
Bit
Stop
Bit
Next
Start
Bit
Idle Frame
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Start
Bit
Stop
Bit
Next
Start
Bit
Start
Bit
Idle Frame
Start
Bit
9-bit Word length (M bit is set)
8-bit Word length (M bit is reset)
Possible
Parity
Bit
Possible
Parity
Bit
Break Frame
Start
Bit
Extra
’1’
Data Frame
Break Frame
Start
Bit
Extra
’1’
Data Frame
Next Data Frame
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