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參數(shù)資料
| 型號： | ST7260E2M1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 38/118頁 |
| 文件大?。?/td> | 2304K |
| 代理商： | ST7260E2M1/XXX |
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ST7260
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8 POWER SAVING MODES
8.1 Introduction
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
After a RESET, the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 (fCPU).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
8.2 HALT Mode
The MCU consumes the least amount of power in
HALT mode. The HALT mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals.
When entering HALT mode, the I bit in the Condi-
tion Code Register is cleared. Thus, all external in-
terrupts (ITi or USB end suspend mode) are al-
lowed and if an interrupt occurs, the CPU clock be-
comes active.
The MCU can exit HALT mode on reception of ei-
ther an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillator is then turned on and a stabi-
lization time is provided before releasing CPU op-
eration. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 17. HALT Mode Flow Chart
N
EXTERNAL
INTERRUPT*
RESET
HALT INSTRUCTION
4096 CPU CLOCK
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
SET
ON
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
OFF
CLEARED
OFF
Y
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
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