參數(shù)資料
型號(hào)： ST72361AR9TC
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, ROHS COMPLIANT, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 55/224頁(yè)
文件大小： 4821K
代理商： ST72361AR9TC
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ST72361-Auto
148/224
LINSCI
SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)
SCICR2 register is set, the LHDM bit selects the
Wake-Up method (replacing the WAKE bit).
0: LIN Synch Break Detection Method
1: LIN Identifier Field Detection Method
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only us-
able in LIN Slave mode.
0: LIN Header Interrupt is inhibited.
1: An SCI interrupt is generated whenever
LHDF = 1.
Bit 1 = LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is
detected and cleared by a software sequence (an
access to the SCISR register followed by a read of
the SCICR3 register). It is only usable in LIN Slave
mode.
0: No LIN Header detected.
1: LIN Header detected.
Notes: The header detection method depends on
the LHDM bit:
– If LHDM = 0, a header is detected as a LIN
Synch Break.
– If LHDM = 1, a header is detected as a LIN
Identifier, meaning that a LIN Synch Break
Field + a LIN Synch Field + a LIN Identifier
Field have been consecutively received.
Bit 0 = LSF LIN Synch Field State
This bit indicates that the LIN Synch Field is being
analyzed. It is only used in LIN Slave mode. In
Auto Synchronization Mode (LASE bit = 1), when
the SCI is in the LIN Synch Field State it waits or
counts the falling edges on the RDI line.
It is set by hardware as soon as a LIN Synch Break
is detected and cleared by hardware when the LIN
Synch Field analysis is finished (See Figure 87).
This bit can also be cleared by software to exit LIN
Synch State and return to idle mode.
0: The current character is not the LIN Synch Field
1: LIN Synch Field State (LIN Synch Field under-
going analysis)
Figure 87. LSF Bit Set and Clear
LIN DIVIDER REGISTERS
LDIV is coded using the two registers LPR and LP-
FR. In LIN Slave mode, the LPR register is acces-
sible at the address of the SCIBRR register and
the LPFR register is accessible at the address of
the SCIETPR register.
LIN PRESCALER REGISTER (LPR)
Read/Write
Reset Value: 0000 0000 (00h)
LPR[7:0] LIN Prescaler (mantissa of LDIV)
These 8 bits define the value of the mantissa of the
LIN Divider (LDIV):
Caution: LPR and LPFR registers have different
meanings when reading or writing to them. Conse-
quently bit manipulation instructions (BRES or
BSET) should never be used to modify the
LPR[7:0] bits, or the LPFR[3:0] bits.
7
0
LPR7
LPR6
LPR5
LPR4
LPR3
LPR2
LPR1
LPR0
LPR[7:0]
Rounded Mantissa (LDIV)
00h
SCI clock disabled
01h
1
...
FEh
254
FFh
255
LIN Synch
Identifier
parity bits
Field
Break
11 dominant bits
LSF bit
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