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參數資料
| 型號： | ST72361AR9TC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, PLASTIC, TQFP-64 |
| 文件頁數： | 132/224頁 |
| 文件大小： | 4821K |
| 代理商： | ST72361AR9TC |
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16 IMPORTANT NOTES
16.1 ALL DEVICES
16.1.1 RESET Pin Protection with LVD Enabled
As mentioned in note 2 below Figure 112 on page
198, when the LVD is enabled, it is recommended
not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise
on the reset line.
16.1.2
Clearing
Active
Interrupts
Outside
Interrupt Routine
When an active interrupt request occurs at the
same time as the related flag or interrupt mask is
being cleared, the CC register may be corrupted.
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, that is, when:
– The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
– The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine
– The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request
Example:
SIM
reset flag or interrupt mask
RIM
Nested interrupt context
The symptom does not occur when the interrupts
are handled normally, that is, when:
– The interrupt request is cleared (flag reset or in-
terrupt mask) within its own interrupt routine
– The interrupt request is cleared (flag reset or in-
terrupt mask) within any interrupt routine with
higher or identical priority level
– The interrupt request is cleared (flag reset or in-
terrupt mask) in any part of the code while this in-
terrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
PUSH CC
SIM
reset flag or interrupt mask
POP CC
16.1.3 External Interrupt Missed
To avoid any risk of generating a parasitic inter-
rupt, the edge detector is automatically disabled
for one clock cycle during an access to either DDR
and OR. Any input signal edge during this period
will not be detected and will not generate an inter-
rupt.
This case can typically occur if the application re-
freshes the port configuration registers at intervals
during runtime.
Workaround
The workaround is based on software checking
the level on the interrupt pin before and after writ-
ing to the PxOR or PxDDR registers. If there is a
level change (depending on the sensitivity pro-
grammed for this pin) the interrupt routine is in-
voked using the call instruction with three extra
PUSH instructions before executing the interrupt
routine (this is to make the call compatible with the
IRET instruction at the end of the interrupt service
routine).
But detection of the level change does ensure that
edge occurs during the critical 1 cycle duration and
the interrupt has been missed. This may lead to
occurrence of same interrupt twice (one hardware
and another with software call).
To avoid this, a semaphore is set to '1' before
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore
status is checked and if it is '1' this means that the
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction.
There is another possible case, that is, if writing to
PxOR or PxDDR is done with global interrupts dis-
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is
done after the global interrupts are enabled (inter-
rupt mask bit reset) and by checking the status of
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
voked with the call instruction.
To implement the workaround, the following soft-
ware sequence is to be followed for writing into the
PxOR/PxDDR registers. The example is for Port
PF1 with falling edge interrupt sensitivity. The soft-
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