參數(shù)資料
型號： ST72171
英文描述： 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述： 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時器SPGAS（軟件可編程增益放大器）。運放
文件頁數(shù)： 61/93頁
文件大?。?/td> 915K
代理商： ST72171
61/93
ST72E121 ST72T121
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
DATA REGISTER (DR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see
Figure 32
).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see
Figure 32
).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
Bit 7:6=
SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bit 5:3 =
SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Note:
this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 =
SCR[2:0]
SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Note:
this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
7
0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
PR Prescaling factor
1
3
4
13
SCP1
0
0
1
1
SCP0
0
1
0
1
TR dividing factor
1
2
4
8
16
32
64
128
SCT2
0
0
0
0
1
1
1
1
SCT1
0
0
1
1
0
0
1
1
SCT0
0
1
0
1
0
1
0
1
RR dividing factor
1
2
4
8
16
32
64
128
SCR2
0
0
0
0
1
1
1
1
SCR1
0
0
1
1
0
0
1
1
SCR0
0
1
0
1
0
1
0
1
61
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