參數(shù)資料
型號(hào): ST72171
英文描述: 8-BIT MCU WITH 8K FLASH. ADC. WDG. SPI. SCI. TIMERS SPGAS (SOFTWARE PROGRAMMABLE GAIN AMPLIFIERS). OP-AMP
中文描述: 8位8K閃存微控制器。 ADC的。水分散粒劑。的SPI。脊髓損傷。定時(shí)器SPGAS(軟件可編程增益放大器)。運(yùn)放
文件頁(yè)數(shù): 10/93頁(yè)
文件大?。?/td> 915K
代理商: ST72171
10/93
ST72E121 ST72T121
Notes:
1. The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
2. External pin not available.
3. Not used in versions without Low Voltage Detector Reset.
0031h
0032h
0033h
0034h-0035h
0036h-0037h
0038h-0039h
003Ah-003Bh
003Ch-003Dh
003Eh-003Fh
Timer A
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
Reserved Area (1 byte)
Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved
SCI Extended Transmit Prescaler Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
2)
Read Only
2)
R/W
2)
R/W
2)
0040h
0041h
0042h
0043h
0044h-0045h
0046h-0047h
0048h-0049h
004Ah-004Bh
004Ch-004Dh
004Eh-004Fh
Timer B
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
C0h
xxh
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
Reserved
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h to
007Fh
SCI
SCIETPR
00x----xb
xxh
00h
00h
---
00h
Reserved Area (40 bytes)
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
10
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