參數(shù)資料
型號(hào)： ST68C454CJ68
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 8/29頁(yè)
文件大小： 184K
代理商： ST68C454CJ68
ST16C454
16
Rev. 3.30
Table 7, INTERRUPT SOURCE TABLE
Priority
[ ISR BITS ]
Source of the interrupt
Level
Bit-3 Bit-2 Bit-1 Bit-0
1
0110
LSR (Receiver Line Status Register)
2
0100
RXRDY (Received Data Ready)
3
0010
TXRDY ( Transmitter Holding Register Empty)
4
0000
MSR (Modem Status Register)
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (See Interrupt Source
Table).
ISR BIT 4-7:
Not used - Initialized to a logic 0.
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.
LCR BIT 0-1: (logic 0 or cleared is the default condi-
tion)
These two bits specify the word length to be transmit-
ted or received.
BIT-1
BIT-0
Word length
00
5
01
6
10
7
11
8
LCR BIT-2: (logic 0 or cleared is the default condition)
The length of stop bit is specified by this bit in conjunc-
tion with the programmed word length.
BIT-2
Word length
Stop bit
length
(Bit time(s))
0
5,6,7,8
1
5
1-1/2
1
6,7,8
2
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity. (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
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