參數(shù)資料
型號： ST62T35B
廠商： 意法半導(dǎo)體
英文描述： 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
中文描述： 8位檢察官辦公室/存儲器與阿微控制器/ D轉(zhuǎn)換器，16位自動重加載定時器，EEPROM中，SPI和UART
文件頁數(shù)： 58/82頁
文件大?。?/td> 617K
代理商： ST62T35B
58/82
ST62T35B/E35B
REGISTERS
(Cont’d)
UART Control Register (UARTCR)
Address: D7h, Read/Write
Bit 7 =
RXRDY.
Receiver Ready This flag be-
comes active as soon as a complete byte has
been received and copied into the receive buffer.
It may be cleared by writing a zero to it. Writing a
one is possible. If the interrupt enable bit RXIEN is
set to one, a software interrupt will be generated.
Bit 6 =
TXMT.
Transmitter Empty This flag be-
comes active as soon as a complete byte has
been sent. It may be cleared by writing a zero to it.
It is automatically cleared by the action of writing a
data value into the UART data register.
Bit 5 =
RXIEN.
Receive Interrupt Enable When
this bit is set to 1, the receive interrupt is enabled.
Writing to RXIEN does not affect the status of the
interrupt flag RXRDY.
Bit 4 =
TXIEN.
Transmit Interrupt Enable When
this bit is set to 1, the transmit interrupt is enabled.
Writing to TXIEN does not affect the status of the
interrupt flag TXRDY.
Bit 3-1=
BR2..BR0
. Baudrate select These bits
select the operating baud rate of the UART, de-
pending on the frequency of fOSC. Care should
be taken not to change these bits during commu-
nication as writing to these bits has an immediate
effect.
Bit 0 =
DAT9
. Parity/Data Bit 9 This bit represents
the 9th bit of the data character that is received or
transmitted. A write to this bit sets the level for the
bit 9 to be transmitted, so it must always be set to
the correct level before transmission. If used as
parity, the value has first to be calculated by soft-
ware. Reading this bit will return the 9th bit of the
received character.
7
0
RXRDY TXMT RXIEN TXIEN
BR2
BR1
BR0
DAT9
57
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