參數(shù)資料
型號(hào): ST62T35B
廠商: 意法半導(dǎo)體
英文描述: 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
中文描述: 8位檢察官辦公室/存儲(chǔ)器與阿微控制器/ D轉(zhuǎn)換器,16位自動(dòng)重加載定時(shí)器,EEPROM中,SPI和UART
文件頁數(shù): 34/82頁
文件大?。?/td> 617K
代理商: ST62T35B
34/82
ST62T35B/E35B
I/O PORTS
(Cont’d)
4.1.2 Safe I/O State Switching Sequence
Switching the I/O ports from one state to another
should be done in a sequence which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions are illustrated inFigure
19.. All other transitions are potentially risky and
should be avoided when changing the I/O operat-
ing mode, as it is most likely that undesirable side-
effects will be experienced, such as spurious inter-
rupt generation ortwopins shorted together by the
analog multiplexer.
Single bit instructions (SET, RES, INC and DEC)
should be used with great caution on Ports Data
registers, since these instructions make an implicit
read and write back of the entire register. In port
input mode, however, the data register reads from
the input pins directly, and not from the data regis-
ter latches. Since data register information in input
mode is used to set the characteristics of the input
pin (interrupt, pull-up, analog input), these may be
unintentionally reprogrammed depending on the
state of the input pins. As a general rule, it is better
to limit the use of single bit instructions on data
registers to when the whole (8-bit) port is in output
mode. In the case of inputs or of mixed inputs and
outputs, it is advisable to keep a copy of the data
register in RAM. Single bit instructions may then
be used on the RAM copy, after which the whole
copy register can be written to the port data regis-
ter:
SET bit, datacopy
LD a, datacopy
LD DRA, a
Care must also be taken to notuse INC or DECin-
structions on a port register when the 8 bits are not
available on the devices.
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuring I/Os in input
mode with well-defined logic levels.
The user must take care not to switch outputs with
heavy loads during the conversion of one of the
analog inputs in order to avoid any disturbance to
the conversion.
Figure 19. Diagram showing Safe I/O State Transitions
Note *.
xxx = DDR, OR, DR Bits respectively
Interrupt
pull-up
Output
Open Drain
Output
Push-pull
Input
pull-up (Reset
state)
Input
Analog
Output
Open Drain
Output
Push-pull
Input
010*
000
100
110
011
001
101
111
33
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