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參數(shù)資料
| 型號(hào)： | st62E18C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with A/D Converter, Auto-Reload Timer, UART, OSG, Safe Reset and 20-Pin Package(8位微控制器(8M)) |
| 中文描述： | 8位微控制器與A / D轉(zhuǎn)換器，自動(dòng)重加載定時(shí)器，UART的秘書長辦公室，安全復(fù)位和20引腳封裝（8位微控制器（8米）） |
| 文件頁數(shù)： | 55/82頁 |
| 文件大小： | 943K |
| 代理商： | ST62E18C |
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ST62T18C/E18C
U. A. R. T
(Cont’d)
4.5.4 Data Reception
The UART continuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time (8
states) to accommodate the Start bit, and then as-
sembles the following serial data stream into the
data register. First 8 bit are stored into the UART
Data Register, while the additionnal 9th bit is
stored into the LSB of the UART Control Register
in case of the 11-bit frame MCU option has been
selected. When the 10-bit frame option is selected,
the parity of the 8 received bit is automatically writ-
ten into the LSB of the UART Control Register
(PTYEN bit).
After all bit have been received, the Receiver waits
for the duration of one bit (for the Stop bit) and
then transfers the received data into the buffer reg-
ister, allowing a following character to be received.
The interrupt flag RXRDY is set to 1 as the data is
transferred to the buffer register and, if enabled,
will generate an interrupt.
Figure 76. Data Sampling Points
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
transmission. This implies that a handshaking sys-
tem must be implemented, as polling of the UART
to detect reception is not available.
4.5.5 Interrupt Capabilities
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enabled by set-
ting TXIEN and RXIEN bit in the UARTCR register,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
4.5.6 Registers
UART Data Register (UARTDR)
Address: D6h, Read/Write
Bit7-Bit0. UART data bits. A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer. If the automatic even parity computation is
set (Bit PTYEN set), D7 must be cleared to 0 be-
fore transmission. Only the 7 LSB D0..D6 contain
the data to be sent.
Warning
. No Read/Write Instructions may be
used with this register as both transmit and receive
share the same address
Table 39. Baudrate Selection
VR02010
1 BIT
0
1
2
3
4
5
6
7
8
SAMPLES
7
0
D7
D6
D5
D4
D3
D2
D1
D0
BR2
BR1
BR0
f
INT
Division
Baud Rate
f
INT
= 8MHz
1200
2400
4800
9600
19200
31200
38400
76800
f
INT
= 4MHz
600
1200
2400
4800
9600
15600
19200
38400
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.656
3.328
1.664
832
416
256
208
104
215
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