參數(shù)資料
型號(hào)： st62E18C
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCUs with A/D Converter, Auto-Reload Timer, UART, OSG, Safe Reset and 20-Pin Package(8位微控制器(8M))
中文描述： 8位微控制器與A / D轉(zhuǎn)換器，自動(dòng)重加載定時(shí)器，UART的秘書長(zhǎng)辦公室，安全復(fù)位和20引腳封裝（8位微控制器（8米））
文件頁數(shù)： 31/82頁
文件大?。?/td> 943K
代理商： ST62E18C
31/82
ST62T18C/E18C
INTERRUPTS
(Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh
—
Read/Write
In conjunction with I/O register ESB bit, the polarity
of I/O pins triggered interrupts can be selected by
setting accordingly the Interrupt Polarity Register
(IPR). If a bit in IPR is set to one the corresponding
port interrupt is inverted (e.g. IPR bit 2 = A; port C
generates interrupt on rising edge. At reset, IPR is
cleared and all port interrupts are not inverted (e.g.
Port C generates interrupts on falling edges).
Bit 7 - Bit 4 = Unused.
Bit 3 = Port D Interrupt Polarity.
Bit 2 = Unused.
Bit 1= Port A Interrupt Polarity.
Bit 0 = Port B Interrupt Polarity.
Tables 31. I/O Interrupts selections according to IPR, IOR programming
7
0
-
-
-
-
PortD
-
PortA PortB
GEN
IPR3
IPR0
IOR5
Port B occurrence
Port D occurrence
Interrupt
source
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
falling edge
rising edge
rising edge
falling edge
falling edge
rising edge
rising edge
falling edge
Disabled
falling edge
rising edge
falling edge
rising edge
rising edge
falling edge
rising edge
falling edge
Disabled
2
GEN
IPR1
IOR6
Port A occurrence
Interrupt
source
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
falling edge
low level
rising edge
high level
Disabled
1
191
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