參數(shù)資料
型號(hào)： st62E18C
廠商： 意法半導(dǎo)體
英文描述： 8-Bit MCUs with A/D Converter, Auto-Reload Timer, UART, OSG, Safe Reset and 20-Pin Package(8位微控制器(8M))
中文描述： 8位微控制器與A / D轉(zhuǎn)換器，自動(dòng)重加載定時(shí)器，UART的秘書(shū)長(zhǎng)辦公室，安全復(fù)位和20引腳封裝（8位微控制器（8米））
文件頁(yè)數(shù)： 50/82頁(yè)
文件大小： 943K
代理商： ST62E18C
50/82
ST62T18C/E18C
AUTO-RELOAD TIMER
(Cont’d)
AR Status Control Register 1(ARSC1)
Address: E7h
—
Read/Write
Bist 7-5 =
PS2-PS0
: Prescaler Division Selection
Bits 2-0. These bits determine the Prescaler divi-
sion ratio. The prescaler itself is not affected by
these bits. The prescaler division ratio is listed in the
following table:
Table 36. Prescaler Division Ratio Selection
Bit 4 =
D4
: Reserved Must be kept reset.
Bit 3-2 =
SL1-SL0
: Timer Input Edge Control Bits 1-
0. These bits control the edge function of the Timer
input pin for external synchronization. If bit SL0 is re-
set, edge detection is disabled; if set edge detection
is enabled. If bit SL1 is reset, the AR Timer input pin
is rising edge sensitive; if set, it is falling edge sen-
sitive.
Bit 1-0 =
CC1-CC0
: Clock Source Select Bit 1-0.
These bits select the clock source for the AR Timer
through the AR Multiplexer. The programming of
the clock sources is explained in the following
Table
37
:
Table 37. Clock Source Selection.
AR Load Register ARLR
. The ARLR load register
is used to read or write the ARTC counter register
“on the fly” (while it is counting). The ARLR regis-
ter is not affected by system reset.
AR Load Register (ARLR)
Address: EBh
—
Read/Write
Bit 7-0 =
D7-D0
: Load Register Data Bits. These
are the load register data bits.
AR Reload/Capture Register
. The ARRC reload/
capture register is used to hold the auto-reload
value which is automatically loaded into the coun-
ter when overflow occurs.
AR Reload/Capture (ARRC)
Address: E9h
—
Read/Write
Bit 7-0 =
D7-D0
: Reload/Capture Data Bits. These
are the Reload/Capture register data bits.
AR Compare Register
. The CP compare register
is used to hold the compare value for the compare
function.
AR Compare Register (ARCP)
Address: EAh
—
Read/Write
Bit 7-0 =
D7-D0
: Compare Data Bits. These are
the Compare register data bits.
7
0
PS2
PS1
PS0
D4
SL1
SL0
CC1
CC0
PS2
0
0
0
0
1
1
1
1
PS1
0
0
1
1
0
0
1
1
PS0
0
1
0
1
0
1
0
1
ARPSC Division Ratio
1
2
4
8
16
32
64
128
SL1
X
0
1
SL0
0
1
1
Edge Detection
Disabled
Rising Edge
Falling Edge
CC1
0
0
1
1
CC0
0
1
0
1
Clock Source
F
int
F
int
Divided by 3
ARTIMin Input Clock
Reserved
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
210
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