參數(shù)資料
型號: ST6242BQ1/XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64
封裝: PLASTIC, QFP-64
文件頁數(shù): 33/69頁
文件大?。?/td> 1846K
代理商: ST6242BQ1/XXX
Obsolete
Product(s)
- Obsolete
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Product(s)
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ST62T42B/E42B
TIMER 1& 2 (Cont’d)
4.2.1 TIMER 1 & 2 Operating Mode
The Timer prescaler is clocked by the prescaler
clock input (fINT ÷ 12).
The user can select for each TIMER the desired
prescaler division ratio through the PS2, PS1, PS0
bits. When the TCR count reaches 0, it sets the
TMZ bit in the TSCR. The TMZ bit can be tested
under program control to perform a timer function
whenever it goes high.
4.2.2 Timer Interrupt
When one of the counter registers decrements to
zero with the associated ETI (Enable Timer Inter-
rupt) bit set to one, an interrupt request is generat-
ed as described in Interrupt Chapter. When the
counter decrements to zero, the associated TMZ
bit in the TSCR register is set to one.
4.2.3 Application Notes
TMZ is set when the counter reaches zero; howev-
er, it may also be set by writing 00h in the TCR
register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
and the timer interrupt is disabled.
A write to the TCR register will predominate over
the 8-bit counter decrement to 00h function, i.e. if a
write and a TCR register decrement to 00h occur
simultaneously, the write will take precedence,
and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
PSC registers can be read accurately at any time.
39
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