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參數(shù)資料
| 型號： | ST6242BQ1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 20/69頁 |
| 文件大?。?/td> | 1846K |
| 代理商： | ST6242BQ1/XXX |
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ST62T42B/E42B
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt Sources
Interrupt
sources
available
on
the
ST62E42B/T42B are summarized in the Table 12
with associated mask bit to enable/disable the in-
terrupt request.
Table 12. Interrupt Requests and Mask Bits
70
-
LES
ESB
GEN
-
Peripheral
Register
Address
Register
Mask bit
Masked Interrupt Source
Interrupt
source
GENERAL
IOR
C8h
GEN
All Interrupts, excluding NMIAll
TIMER 1
TIMER 2
TSCR1
TSCR2
D4h
D7h
ETI
TMZ: TIMER Overflow
source 3
A/D CONVERTER
ADCR
D1h
EAI
EOC: End of Conversion
source 4
SPI
C2h
ALL
End of Transmission
source 1
Port PAn
ORPA-DRPA
C0h-C4h
ORPAn-DRPAn
PAn pin
source 2
Port PBn
ORPB-DRPB
C1h-C5h
ORPBn-DRPBn
PBn pin
source 2
Port PCn
ORPC-DRPC
C6h-CFh
ORPCn-DRPCn
PCn pin
source 2
27
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