參數(shù)資料
型號: ST6235BQ1
廠商: 意法半導(dǎo)體
英文描述: 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
中文描述: 8位檢察官辦公室/存儲器與阿微控制器/ D轉(zhuǎn)換器,16位自動重加載定時(shí)器,EEPROM中,SPI和UART
文件頁數(shù): 43/82頁
文件大?。?/td> 617K
代理商: ST6235BQ1
43/82
ST62T35B/E35B
4.3.1 CENTRAL COUNTER
The core of the 16 bit Auto-Reload Timer is a 16-
bit synchronous downcounter which accepts the
MCU internal clock through a prescaler with a pro-
grammable ratio (1/1, 1/4, 1/16).
The maximum time for downcounting is therefore
2
16
x Psc x Tclk where Psc is the prescaler ratio,
and Tclk the period of the main oscillator.
This down counter is stopped and its content kept
cleared as long as RUNRES bit is cleared.
4.3.1.1 Reload functions
The 16-bit down counter can be reloaded 3 differ-
ent ways:
At azero overflow occurrence with thebit RELOAD
cleared: The counter is reloaded to FFFFh.
At a zero overflow occurrence with the bit
RELOAD set: The counter is reloaded with the val-
ue programmed in the RLCP register. For each
overflow, the transition between 0000h and the re-
load value (RLCP or FFFFh) is flagged through
the OVFFLG bit.
At an external event on pin CP1 or CP2 with the bit
RELOAD set: The counter is reloaded with the val-
ue programmed in the RLCP register.
As a consequence, the time between a timer re-
load and a zero overflow occurrence depends on
the value in RLCP when RELOAD bit is set. This
time is equal to (RLCP+1) x Psc x Tclk when
RELOAD bit is set, while it is 2
16
x Psc x Tclk
when RELOAD bit is cleared.
4.3.1.2 Compare functions
The value in the counter CT is continuously com-
pared to 0000h and to the value programmed into
the Compare Register CMP. The comparison
range to 0000h and CMP is defined by using the
MASK register to select which bits are used,
therefore the comparisons performed are:
– MASK&CT =
MASK&CMP.
– MASK&CT =0000h.
When
a matched
comparison
MASK&CMP occurs, the flags ZEROFLG and
COMPFLG are respectively set.
By using MASK values reported inTable 16., the
MASK register works as counter frequency multi-
plier for the compare functions. In that case posi-
tive masked comparison occur with a period of
2
(n+1)
x Psc x Tclk where n is the position of the
most significant bit of MASK value.
Table 16..Recommended Mask Values
to 0000h
or
Note
: Writing 0000h in MASK gives a period equal
to two times the prescaled period Psc x Tclk.
Figure 24. . Flags Setting in Compare and Reload Functions
Hexadecimal
Binary
MSbit at 1
position,n
15
14
13
12
11
FFFFh
7FFFh
3FFFh
1FFFh
0FFFh
...
0007h
0003h
0001h
1111 1111 1111 1111
0111 1111 1111 1111
0011 1111 1111 1111
0001 1111 1111 1111
0000 1111 1111 1111
...
0000 0000 0000 0111
0000 0000 0000 0011
0000 0000 0000 0001
2
1
0
CMP
Counter
Value CT
ZEROFLG
0
FFFFh
or
RLCP
Software Reset
Software Reset
Software Reset
OVFFLG
COMPFLG
42
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