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參數(shù)資料
| 型號： | ST16C654IQ64/TR |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64 |
| 文件頁數(shù)： | 30/54頁 |
| 文件大?。?/td> | 734K |
| 代理商： | ST16C654IQ64/TR |
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ST16C654/654D
REV. 5.0.2
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
33
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character
has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the
compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR
register. The CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this
bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input
when the modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is
equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the
modem interface is not used.
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the
modem interface is not used.
4.10
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11
Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.12
Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
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相關代理商/技術參數(shù) |
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| ST16C654IQ64TR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 64-Pin LQFP T/R 制造商:Exar Corporation 功能描述:ST16C654IQ64TR-F |
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