參數(shù)資料
型號(hào): ST16C654IQ64/TR
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁數(shù): 11/54頁
文件大?。?/td> 734K
代理商: ST16C654IQ64/TR
ST16C654/654D
xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.2
16
2.11
Auto RTS Hardware Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 11):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If needed, the RTS interrupt can be enabled through IER bit-6 (after setting EFR bit-4). The UART issues an
interrupt when the RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.12
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
Enable auto CTS flow control using EFR bit-7.
If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an
interrupt when the CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend
transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after
the CTS# input is re-asserted (logic 0), indicating more data may be sent.
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
E
rror
T
ags
(64-
sets)
E
rro
rTa
gs
in
LSR
b
its
4
:2
64 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO
Trigger=16
Example
:
- RX FIFO trigger level selected at 16 bytes
Data fills to
56
Data falls to
8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
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