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參數(shù)資料
| 型號： | ST16C650AIP40 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| 中文描述： | 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 16/53頁 |
| 文件大?。?/td> | 666K |
| 代理商： | ST16C650AIP40 |
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ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
á
REV. 5.0.0
16
2.10
The receiver section contains an 8-bit Receive Shift Register (RSR) and 32 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in the RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay
until it reaches the FIFO trigger level (XFR bit-3). Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.10.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 32 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
Receiver
F
IGURE
11. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
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PDF描述 |
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| ST16C650AIQ48 | 2.90V TO 5.5V UART WITH 32-BYTE FIFO |
| ST16C650 | Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Output Current:350mA; Output Voltage:3.3V; Current Rating:30.05A; Leaded Process Compatible:Yes; Output Voltage Max:3.3V RoHS Compliant: Yes |
| ST26C32CF16 | QUAD RS-422, RS-423 CMOS Differential Line Receiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C650AIQ48 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:UART, 48 Pin, Plastic, TQFP |
| ST16C650AIQ48-F | 功能描述:UART 接口集成電路 UART W/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C650AIQ48TR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C650AIQ48TR-F | 功能描述:UART 接口集成電路 UART W/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C650CJ44 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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