參數(shù)資料
型號： ST16C650AIJ44
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.90V TO 5.5V UART WITH 32-BYTE FIFO
中文描述： 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 53/53頁
文件大?。?/td> 666K
代理商： ST16C650AIJ44
á
REV. 5.0.0
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
II
4.1 R
ECEIVE
H
OLDING
R
EGISTER
(RHR) - R
EAD
-O
NLY
............................................................................ 25
4.2 T
RANSMIT
H
OLDING
R
EGISTER
(THR) - W
RITE
-O
NLY
......................................................................... 25
4.3 I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/W
RITE
.......................................................................... 25
4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 25
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 26
4.4 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
-O
NLY
............................................................................ 27
4.4.1 Interrupt Generation:................................................................................................................................ 27
4.4.2 Interrupt Clearing: .................................................................................................................................... 27
4.5 FIFO C
ONTROL
R
EGISTER
(FCR) - W
RITE
-O
NLY
............................................................................... 28
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
............................................................................................................................... 28
4.6 L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
................................................................................ 29
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
WITH
AUTO
RTS
HYSTERESIS
....................................................... 29
T
ABLE
11: P
ARITY
SELECTION
................................................................................................................................................................ 30
4.7 M
ODEM
C
ONTROL
R
EGISTER
(MCR)
OR
G
ENERAL
P
URPOSE
O
UTPUTS
C
ONTROL
- R
EAD
/W
RITE
....... 31
4.8 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
..................................................................................... 32
4.9 E
XTRA
F
EATURE
R
EGISTER
(XFR) - W
RITE
O
NLY
.............................................................................. 33
4.10 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
............................................................................. 34
4.11 I
NFRARED
T
RANSMIT
P
ULSE
W
IDTH
C
ONTROL
R
EGISTER
(IRPW) - W
RITE
O
NLY
............................. 35
4.12 S
CRATCH
P
AD
R
EGISTER
(SPR) ..................................................................................................... 35
4.13 B
AUD
R
ATE
G
ENERATOR
D
IVISORS
(DLL
AND
DLM) - R
EAD
/W
RITE
................................................. 35
4.14 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
................................................................. 35
4.15 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
......................................................................... 35
4.16 E
NHANCED
F
EATURE
R
EGISTER
(EFR) ............................................................................................ 35
T
ABLE
12: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
............................................................................................................................... 36
4.17 S
OFTWARE
F
LOW
C
ONTROL
R
EGISTERS
(XOFF1, XOFF2, XON1, XON2) - R
EAD
/W
RITE
............... 37
T
ABLE
13: UART RESET CONDITIONS ............................................................................................................................................. 38
ELECTRICAL CHARACTERISTICS................................................................................39
DC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................39
AC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................40
TA=0
O
TO
70
O
C (-40
O
TO
+85
O
C
FOR
INDUSTRIAL
GRADE
PACKAGE
), V
CC
IS
2.90V
TO
5.5V, 70
P
F L
OAD
WHERE
APPLICABLE
40
F
IGURE
16. C
LOCK
T
IMING
.................................................................................................................................................................... 42
F
IGURE
17. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
............................................................................................................................................ 42
F
IGURE
18. D
ATA
B
US
R
EAD
T
IMING
IN
I
NTEL
B
US
M
ODE
WITH
AS#
TIED
TO
GND................................................................................. 43
F
IGURE
19. D
ATA
B
US
W
RITE
T
IMING
IN
I
NTEL
B
US
M
ODE
WITH
AS#
TIED
TO
GND ............................................................................... 43
F
IGURE
20. D
ATA
B
US
R
EAD
T
IMING
IN
I
NTEL
B
US
M
ODE
USING
AS#..................................................................................................... 44
F
IGURE
21. D
ATA
B
US
W
RITE
T
IMING
IN
I
NTEL
B
US
M
ODE
USING
AS#................................................................................................... 44
F
IGURE
22. D
ATA
B
US
R
EAD
T
IMING
IN
PC M
ODE
................................................................................................................................. 45
F
IGURE
23. D
ATA
B
US
W
RITE
T
IMING
IN
PC M
ODE
................................................................................................................................ 45
F
IGURE
24. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
] ................................................................................................... 46
F
IGURE
25. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
] ................................................................................................. 46
F
IGURE
26. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
].................................................................................. 47
F
IGURE
27. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
] .................................................................................. 47
F
IGURE
28. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
] ..................................................................... 48
F
IGURE
29. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
] ...................................................................... 48
P
ACKAGE
D
IMENSIONS
(48
PIN
TQFP
- 7
X
7
X
1
MM
) .................................................................................49
P
ACKAGE
D
IMENSIONS
(44
PIN
PLCC)......................................................................................................50
R
EVISION
H
ISTORY
....................................................................................................................................51
TABLE OF CONTENTS ................................................................................................................................. I
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