參數(shù)資料
型號(hào)： ST16C650AIJ44
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.90V TO 5.5V UART WITH 32-BYTE FIFO
中文描述： 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 18/53頁(yè)
文件大小： 666K
代理商： ST16C650AIJ44
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
á
REV. 5.0.0
18
2.13
When software flow control is enabled (
See Table 12
), the 650A compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If received character(s) (RX) match the
programmed values, the 650A will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character values, the 650A will monitor
the receive data stream for a match to the Xon-1,2 character value(s). If a match is found, the 650A will resume
operation and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (
See Table 12
) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
selected, the 650A compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
Auto Xon/Xoff (Software) Flow Control
F
IGURE
13. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
RTSA#
CTSB#
RXA
TXB
Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON
OFF
ON
Suspend
Restart
RTS High
Threshold
Data Starts
ON
OFF
ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data
RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#
CTSA#
RXB
TXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
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ST16C650AIQ48TR 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
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