參數(shù)資料
型號(hào)： ST16C650ACQ48
廠(chǎng)商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2.90V TO 5.5V UART WITH 32-BYTE FIFO
中文描述： 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 52/53頁(yè)
文件大小： 666K
代理商： ST16C650ACQ48
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
á
REV. 5.0.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
F
EATURES
...................................................................................................................................................1
A
PPLICATIONS
.............................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
..................................................................................................................................................................... 1
F
IGURE
2. I
NTEL
AND
PC
MODE
P
IN
O
UT
................................................................................................................................................. 2
PIN DESCRIPTIONS ........................................................................................................3
ORDERING
INFORMATION
..............................................................................................................................3
1.0 Product Description ............................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................. 8
2.1 H
OST
D
ATA
B
US
I
NTERFACE
................................................................................................................ 8
F
IGURE
3. ST16C650A I
NTEL
B
US
I
NTERCONNECTIONS
.......................................................................................................................... 8
F
IGURE
4. ST16C650A M
OTOROLA
B
US
I
NTERCONNECTIONS
.................................................................................................................. 9
F
IGURE
5. ST16C650A PC M
ODE
I
NTERCONNECTIONS
........................................................................................................................... 9
2.1.1 PC MODE................................................................................................................................................. 10
T
ABLE
1: PC M
ODE
I
NTERFACE
O
N
-
CHIP
A
DDRESS
D
ECODER
AND
I
NTERRUPT
S
ELECTION
. .................................................................... 10
F
IGURE
6. PC M
ODE
I
NTERFACE
IN
AN
E
MBEDDED
A
PPLICATION
............................................................................................................ 10
2.2 5-V
OLT
T
OLERANT
I
NPUTS
................................................................................................................. 11
2.3 D
EVICE
R
ESET
.................................................................................................................................. 11
2.4 D
EVICE
I
DENTIFICATION
AND
R
EVISION
............................................................................................... 11
2.5 DMA M
ODE
...................................................................................................................................... 11
T
ABLE
2: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
.................................................................................................. 11
2.6 I
NTERRUPT
........................................................................................................................................ 12
T
ABLE
3: I
NTERRUPT
O
UTPUT
(INT
AND
IRQA) F
UNCTIONS
................................................................................................................... 12
2.7 C
RYSTAL
O
SCILLATOR
OR
E
XTERNAL
C
LOCK
...................................................................................... 13
2.8 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
......................................................................................... 13
F
IGURE
7. T
YPICAL
OSCILLATOR
CONNECTIONS
...................................................................................................................................... 13
2.9 T
RANSMITTER
.................................................................................................................................... 14
F
IGURE
8. B
AUD
R
ATE
G
ENERATOR
....................................................................................................................................................... 14
T
ABLE
4: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
.............................................................................. 14
2.9.1 Transmit Holding Register (THR) - Write Only......................................................................................... 15
2.9.2 Transmitter Operation in non-FIFO Mode ................................................................................................ 15
2.9.3 Transmitter Operation in FIFO Mode........................................................................................................ 15
F
IGURE
9. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
...................................................................................................................... 15
F
IGURE
10. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
........................................................................................... 15
2.10 R
ECEIVER
....................................................................................................................................... 16
2.10.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 16
F
IGURE
11. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
......................................................................................................................... 16
2.11 A
UTOMATIC
RTS (H
ARDWARE
) F
LOW
C
ONTROL
............................................................................... 17
2.12 A
UTO
CTS F
LOW
C
ONTROL
............................................................................................................. 17
F
IGURE
12. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
............................................................................... 17
2.13 A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
................................................................................ 18
F
IGURE
13. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
.............................................................................................................. 18
2.14 S
PECIAL
C
HARACTER
D
ETECT
......................................................................................................... 19
2.15 A
UTO
RS485 H
ALF
-
DUPLEX
C
ONTROL
............................................................................................ 19
T
ABLE
5: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
....................................................................................................................... 19
T
ABLE
6: RS485 H
ALF
-D
UPLEX
C
ONTROL
............................................................................................................................................. 19
2.16 I
NFRARED
M
ODE
............................................................................................................................. 20
F
IGURE
14. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
................................................................................. 20
2.17 S
LEEP
M
ODE
& W
AKE
-
UP
I
NDICATOR
............................................................................................... 21
2.17.1 Sleep Mode in IR Mode.......................................................................................................................... 21
2.18 I
NTERNAL
L
OOPBACK
....................................................................................................................... 22
F
IGURE
15. I
NTERNAL
L
OOP
B
ACK
......................................................................................................................................................... 22
3.0 UART CONFIGURATION REGISTERS ................................................................................. 23
T
ABLE
7: ST16C650A UART CONFIGURATION REGISTERS .......................................................................................................... 23
T
ABLE
8: UART CONFIGURATION REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1........................... 24
4.0 Internal register descriptions .............................................................................................. 25
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