參數(shù)資料
型號(hào): ST16C650ACQ48
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.90V TO 5.5V UART WITH 32-BYTE FIFO
中文描述: 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁數(shù): 31/53頁
文件大?。?/td> 666K
代理商: ST16C650ACQ48
á
REV. 5.0.0
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
31
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected if
LCR
0xBF
.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used for
general purpose.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Pins
The RTS# pin is a modem control output and may be used for automatic hardware flow control enabled by
EFR bit-6. If the modem interface is not used, this output may be used for general purpose.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: OP1# Output
OP1# is a general purpose output.
Logic 0 = OP1# output is at logic 1 (default).
Logic 1 = OP1# output is at logic 0
MCR[3]: OP2# or IRQn Enable during PC Mode
OP2# is a general purpose output available during the Intel or Motorola bus interface mode of operation. In the
PC bus mode, it enables the IRQn operation. See PC Mode section.
During Intel or Motorola Bus Mode Operation:
Logic 0 = OP2# output is at logic 1 (default).
Logic 1 = OP2# output is at logic 0.
During PC Mode Operation:
Logic 0 = Disable IRQn operation (default).
Logic 1 = Enable IRQn operation.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Figure 15
.
MCR[5]: Active/Three-state Interrupt Output Enable
Logic 0 = Enable active or three-state interrupt output (default).
Logic 1 = Enable open source interrupt output mode. See
Table 3
for detailed information.
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