參數(shù)資料
型號(hào)： ST16C650ACQ48
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.90V TO 5.5V UART WITH 32-BYTE FIFO
中文描述： 1 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 29/53頁(yè)
文件大小： 666K
代理商： ST16C650ACQ48
á
REV. 5.0.0
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
29
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins.
See “DMA Mode” on page 11.
Logic 0 = DMA Mode disabled (default).
Logic 1 = DMA Mode enabled.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last re-load.
Table 10
below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1).
The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the
receiver FIFO interrupt.
Table 10
shows the complete selections..
4.6
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
Line Control Register (LCR) - Read/Write
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
WITH
AUTO
RTS
HYSTERESIS
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
T
RANSMIT
INT
T
RIGGER
L
EVEL
R
ECEIVE
INT
T
RIGGER
L
EVEL
A
UTO
RTS
D
E
-
ASSERT
A
UTO
RTS
R
E
-
ASSERT
C
OMPATIBILITY
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
16
8
24
30
8
16
24
28
16
24
28
28
0
8
16
24
16C650A compati-
ble.
BIT-1
BIT-0
W
ORD
LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
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