![](http://datasheet.mmic.net.cn/370000/ST16C1450_datasheet_16733411/ST16C1450_7.png)
á
REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
7
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
1.0
PRODUCT DESCRIPTION
The ST16C145X provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required in digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The 145X is capable of
operation up to 1.5 Mbps with a 24 MHz crystal or external clock input with a 16X sampling clock (at VCC =
5.0V). With a crystal of 14.7456 MHz and through a software option, the user can select data rates up to 921.6
Kbps.
2.0
FUNCTIONAL DESCRIPTIONS
2.1
The 145X has a set of enhanced registers for controlling, monitoring and data loading and unloading. These
registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO
control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers
(MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpad
register (SPR). All the register functions are discussed in full detail later in
“Section 3.0, UART INTERNAL
REGISTERS” on page 13
.
Internal Registers
GND
15
14
15
14
19
Pwr
Power supply common ground.
N.C.
-
-
-
-
1, 2,
10-14,
18,
24-26,
29,
35-38,
42, 44,
48
-
Not connected.
N
AME
28-P
IN
PDIP
(1450)
28-P
IN
PDIP
(1451)
28-P
IN
PLCC
(1450)
28-P
IN
PLCC
(1451)
48-P
IN
TQFP
(145X)
T
YPE
D
ESCRIPTION