參數(shù)資料
型號(hào)： ST10F168-Q3
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144
封裝： 28 X 28 MM, PLASTIC, QFP-144
文件頁數(shù)： 60/74頁
文件大?。?/td> 479K
代理商： ST10F168-Q3
ST10F168
63/74
20.5.11 - Demultiplexed Bus
VDD =5V ±10%, VSS = 0V, for Q6 version : TA =-40, +85°C and for Q3 version TA = -40, +125°C, CL = 100pF,
ALE cycle time = 4 TCL + 2tA +tC +tF (80ns at 25MHz CPU clock without wait states), unless otherwise
specified.
Table 25 : Demultiplexed bus characteristics
Symbol
Parameter
Maximum
CPU Clock = 25MHz
Variable CPU Clock
1/2 TCL = 1 to 25MHz
Unit
Minimum
Maximum
Minimum
Maximum
t5
CC ALE high time
10 + tA
–
TCL - 10+ tA
–ns
t6
CC Address setup to ALE
4 + tA
–
TCL - 16+ tA
–ns
t80 CC Address / Unlatched CS setup to
RD, WR (with RW-delay)
30 + 2tA
–
2TCL - 10 + 2tA
–ns
t81 CC Address / Unlatched CS setup to
RD, WR (no RW-delay)
10 + 2tA
–
TCL -10 + 2tA
–ns
t12 CC RD, WR low time (with
RW-delay)
30 + tC
–
2TCL - 10 + tC
–ns
t13 CC RD, WR low time (no RW-delay)
50 + tC
–
3TCL - 10 + tC
–ns
t14 SR RD to valid data in (with
RW-delay)
–20 + tC
–2TCL - 20 + tC
ns
t15 SR RD to valid data in (no
RW-delay)
–40 + tC
–3TCL - 20 + tC
ns
t16 SR ALE low to valid data in
–
40 + tA +tC
–
3TCL - 20
+tA +tC
ns
t17 SR Address / Unlatched CS to valid
data in
–50 + 2tA +tC
–
4TCL - 30
+2tA +tC
ns
t18 SR Data hold after RD rising edge
0
–
0
–
ns
t20 SR Data float after RD rising edge
(with RW-delay)12
–26 + tF
–
2TCL - 14
+tF +2tA
1
ns
t21 SR Data float after RD rising edge
(no RW-delay)12
–10 + tF
–TCL - 10
+tF +2tA
1
ns
t22 CC Data valid to WR
20 + tC
–
2TCL- 20 + tC
–ns
t24 CC Data hold after WR
10 + tF
–TCL - 10+ tF
–ns
t26 CC ALE rising edge after RD, WR
-10 + tF
–-10 + tF
–ns
t28 CC Address / Unlatched CS hold after
RD, WR
3
0(no tF)
-5 + tF
(tF >0)
–
0 (no tF)
-5 + tF (tF >0)
–ns
t28h CC Address / Unlatched CS hold
after WRH
-5 + tF
–-5 + tF
–ns
t38 CC ALE falling edge to Latched CS
-4 - tA
10 - tA
-4 - tA
10 - tA
ns
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