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參數(shù)資料
| 型號： | ST10F168-Q3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 28 X 28 MM, PLASTIC, QFP-144 |
| 文件頁數(shù)： | 49/74頁 |
| 文件大小： | 479K |
| 代理商： | ST10F168-Q3 |
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ST10F168
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6. During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference
voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results
from the programmed conversion timi ng.
7. Partially tested, guaranteed by design characterization.
8. To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at
the ADC input. The cut-off frequency of this filter must be twice the highest conversion frequency used in the application as described
in the formula:
fcut-off =2 / tc app
where tc app is the shorter conversion time used in the application, calculated with the following formula:
tc app =14 tCC +tS + 4 TCL (= 14 tCC +2 tSC + 4 TCL).
ADC Sample time and conversion time are programmable. The table below should be used to calculate
the above timings.
20.5 - AC Characteristics
20.5.1 - Test Waveforms
Conversion Time
Sample Time
ADCON.15|14 (ADCTC)
Conversion clock tCC
ADCON.13|12 (ADSTC)
Sample clock tSC
00
TCL x 24
00
tCC
01
Reserved, do not use
01
tCC x2
10
TCL x 96
10
tCC x4
11
TCL x 48
11
tCC x8
Figure 16 : Input / output waveforms
Figure 17 : Float waveforms
2.4V
0.45V
Test Points
0.2VDD+0.9
0.2VDD-0.1
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
Timing
Reference
Points
VLoad +0.1V
VLoad -0.1V
VOH -0.1V
VOL +0.1V
VLoad
VOL
VOH
For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.
It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).
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